UDP and making progress.

My VHDL guru contact at UBC has been helping me out a fair deal with getting off the ground with an Ethernet interface for the FPGA. At this point, I at least know what keywords to look for. Also, after discussing it a bit, I decided to go with UDP rather than TCP as my transfer protocol as it is worlds simpler to implement. I may have to do some reordering once the packets are read in by the PC, but given the fact that I'm working with 10G Ethernet, I've got enough bandwidth to add things like a packet counter, for example. 

According to him, on a clean network, packet loss is also less than 1%, which is fine. I'm expecting to be reading out numbers every 100ns, which gives me an order of magnitude higher temporal resolution (100ns vs 2.5 microseconds) than H.E.S.S. had when they first tired the experiment is based on, so losing one or two packets won't neccisarily degrade the signal too much.

If I understand the issue correctly, I may have a workaround for the fact that my embedded processor peripherals don't work. Essentially, it comes down to VHDL being a 'dumb' programming language. Regardless, correcting for this has created a new error (whoohoo) that simply has to do with syntax, and should be resolved shortly.