the one that started 7 days ago, the purest sense of the word 'week',
but I digress).
Worked out all my software kinks for CAEN. I just need to get the
hardware to lower its thresholds, for which I have sent an email to
the wonderful Italians that absolutely love helping me debug their
hardware.
FPGA stuff is a little slow. VHDL is a really weird programming
language. Also, albeit the fact that I found an example doing
precisely what I want to be doing now, the code is barely commented,
so it's going to be tricky to figure out what's what.
Day's over soon. The sun's come out.
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