Mission Accomplished.

Every programmer knows that often a single character typo can make a
huge difference.

In this case, a missing '=' was what was keeping me (and presumably
anyone else using a V1718 USB bridge) from taking data. This line of code:

while ( ((long)(data_size-=4) >0) && (( read_events<
user_setting.m_num_events)|| (user_setting.m_num_events<= 0)))

is very complicated. So lets look at the important part:

while( ((long) (datasize-=4) > 0 .... )

This line subtracts 4 from the data_size value and checks to see if
the result is greater than zero. The effect is that when the data_size
variable is AT zero, the code stops executing. What this ends up doing
is cutting off the data acquisition process before the last line gets
out, and (in my experience) is a common mistake. Usually it would
read:

while( ((long) (datasize-=4) >= 0 .... )

which would execute it one last time when it has reached zero.

So I was thinking about this this morning when I received an email
from technicians in Italy:

"Hello Sean...

I did the test yesterday, finding your same problem: it is a software
bug and today we have found the solution.

Unfortunately, the person responsible for the software is traveling for work.
Then we will release the new software release (corrected) to return
from teh summer holidays at the end of August.

In the meantime, I tell you the problem.
I believe that you have not any problems to correct the source and
recompile all.

At line 485 of file maic.c you can find

>>>> while ( ((long)(data_size-=4) >0) && (( read_events< user_setting.m_num_events)|| (user_setting.m_num_events<= 0)))

You have to change it like this:

>>>> while ( ((long)(data_size-=4) >= 0) && (( read_events< user_setting.m_num_events)|| (user_setting.m_num_events<= 0)))

In the old version simply the last word transferred with the BLT was
not controlled and stored in the file. [...]"

...It would seem as though I discovered a major flaw in this companies
software, before their technicians did.

Everything is fine and dandy now. I can look at muon shapes to my
heart's content. I will be taking a data set over the weekend.

The best part is, I spent so much time waiting for them to get back to
me that I had already programmed the rest of the infrastructure. So
now all I need to do is take data. w00t.

Late for the first time.

As I boarded the train this morning, the conductor informed us that
there was a power outage at a station halfway down the track and we
were going to stop in the Waste, err, West Island and wait for
instructions. 45 minutes later (as I should have been sitting down in
my office) we were informed that there were busses on the way to take
us to the metro. 30 minutes later we boarded the metro and took it
from Cote-Vertu all the way to Bonneaventure. Then it was a quick skip
and a hop to the group meeting where I kindly interrupted the girl who
was presenting.

Luckily, my boss had received the SMS emails I had sent him over the
day and it was embarrassment more than anything. But still. Broke my
perfect record. Damn train.

There is a power outage on the train and I have a group meeting at 10 to go to. Boy, oh boy.
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A C-String-esque situation.

This is a conversation I just had with one of my friends.

kim? says:
http://dlisted.com/node/33176
hahahaha
i love it

Sean says:
Wtf, Kim, I'm in my office, lol,
You have to NSFW that shit,

kim? says:
hahahaha
hahahaha

--
-=//\=-

I got the FPGA blues.

I think at this point I may have bitten off more than I can chew, at
least for the time being. I think what I'm trying to do is build the
CN tower when all I've ever done is play with Lego. Which is a bit
uncool.

I'm missing one bit of information: I can't for the life of me figure
out how to tie the embedded processor code to the VHDL scripts I have
. The embedded processor is what will host the data (web) server, and
the VHDL actually takes the data. I know it's possible to do this, I
just can't for the life of me find a reference.

Back to work.

Whats the point in walking your dog if youre going to carry it?
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The best part about the train is when someone is happy because its early and really its just not late.
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Talk about abstract.

If you google 'ML402 Web Server', the 6th entry down as I write this
entry is actually my previous post.

Today there was more talk about going back to Arizona in August,
likely right before classes start. We've got someone going down to
align T1, and I'd really like to contribute.

I'm slowly making progress in my understanding of the Xilinx EDK (for
the FPGA stuff). In a nutshell, I'm trying to install a Linux-based
web server on this ML402 board that will allow me to read out data
from the rate counters (which also need to be designed but that's the
'easy' part). All this combined will allow me to plug into one of the
telescopes (likely starting with the Whipple 10m for debugging
purposes) and take data read out to a computer.

The ML402 board I'm using has 64MB of DDR SDRAM. Assuming 20% of that
will be taken up by the operating system, I'm hoping that the
remaining 50MB is enough space to contain the data. The idea is that
even though we'll be reading in values very quickly (microsecond
timespans) if we have a large memory buffer we can read off of
periodically at a high speed. In other words, the computer can't read
and store data on a microsecond timespan, but is able to read and
store a large amount of data every second or so, say.

A bad case of the Mondays.

It would seem as though my morning routine recently can be brought
down to pulling out 40 thousand PDFs on FPGA programming and trying
the single command that the technician at CAEN wants me to try. When
the latter fails, I try to figure out why, wonder about it for awhile,
then email back the failure with a question as to whether or not it
could be (e.g.) the firmware.

Naturally, I wont actually get an answer to the question, I'll get a
completely unrelated quote from the manual in response.

Hell hath no fury like a CAEN technician.

As I write this we are 14:52 away from the 40th anniversary of the
Apollo 11 landing. I've heard alot of conspiracy theorists asking
radio hosts if they thought it was faked, and other people complaining
about how there are a billion Chinese kids starving to death in Africa
and therefore we should go back in time and cut the NASA budget in
order to help this problem.

I think they're a bunch of morons, but that's me.

There were some interesting pictures released from the LRO (Lunar
Reconnaissance Orbiter) of the Apollo landing sites,
http://www.nasa.gov/mission_pages/LRO/multimedia/lroimages/apollosites.html
.

Of course, these were photoshopped by the same guys who set the sounds
tage in Nevada to fake the landing. </sarcasm>

Today, I taught the FPGA to write to its SRAM memory. Next task is a
rate counter that will store the rate to memory.

I just watched the STS-127 crew walkout (again). Weather is still NO
GO for launch.

I also tried to test out this new FPGA module I wrote for reading /
writing memory, but no one was in the Cosmology lab downstairs so I
couldn't get my hands on the Spartan board to test it out. There's
something hokey going on in the simulation that I'm not entirely
convinced would be replicated in real life.

In the picture, you can see that the led[7:0] segment (which should
come up as a number between 0 and 255 inclusive) is coming up as 'ZZ'.
I could understand maybe the data input/output buffer doing something
weird (which it is), but the led output is purely either on or off,
and in most circumstances chooses not to be a set of letters or
shapes.

Too chilly for shorts today. cant wait to get home and change.
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Slow.

OK, so it's been a slow week (not the one that just started, I mean,
the one that started 7 days ago, the purest sense of the word 'week',
but I digress).

Worked out all my software kinks for CAEN. I just need to get the
hardware to lower its thresholds, for which I have sent an email to
the wonderful Italians that absolutely love helping me debug their
hardware.

FPGA stuff is a little slow. VHDL is a really weird programming
language. Also, albeit the fact that I found an example doing
precisely what I want to be doing now, the code is barely commented,
so it's going to be tricky to figure out what's what.

Day's over soon. The sun's come out.

Things I've just heard: 'What the hell, I'm not your scott towel!'
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With the exception of one discriminator channel, I didn't lose any
hardware today. Noticed I was making a bit of a stupid mistake with
something, but other than that, all is well.

--
-=//\=-

Mission.

Today if no more of my hardware breaks, I'll be able to start taking
data for the muon experiment, the culmination of 7 weeks of work.

Of course, this hinges entirely on the assumption that now that the
CAEN hardware works porperly, I haven't the need to keep mucking
around with it.

Back in the lab. Had another discriminator channel die today. Still no
clues as to the culprit. I've been following Brent Spiner on Twitter,
he's rather entertaining.

Currently, I'm working on some code that will allow the FPGA to take
an input and calculate its square root. Needs to be done iteratively,
which makes it a little bit tricky.

Steak for supper tonight, I'm thinking mushroom sauce.

Sucked in.

New Twitter account, username astroGriff.

Why is so much of my hardware going?

Somehow, another discriminator channel went today (that makes six or
seven) which meant that I had to track down another. This one is fully
functional on all channels, so if it starts to go, I'm going to have
to assume that maybe the NIM bin power supply is konking out on that
particular slot. but testing for that might be hairy.